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aolofsson / awesome-hardware-tools

  • воскресенье, 17 апреля 2022 г. в 00:31:22
https://github.com/aolofsson/awesome-hardware-tools


List of awesome open source hardware tools



awesome-hardware-tools

A curated list of awesome open source hardware tools.

  • Categorized
  • Alphabetical (per category)
  • Requirements
    • link should be to source code repository
    • open source projects only
    • working projects only (not WIP/rusty)
  • One tag line sentence per project.

Compiler Frameworks

  • act
    • Asynchronous circuit compiler tools
  • amaranth
    • Python based hardware design framework
  • bsc
    • Compiler, simulator, and tools for the Bluespec Hardware Description Language
  • calyx
    • Intermediate language and infrastructure for building compilers that generate custom hardware accelerators
  • chisel
    • Scala based hardware description language
  • circt
    • Circuit IR Compilers and Tools
  • circuitgraph
    • Tools for working with circuits as graphs in python
  • clash
    • Haskell to VHDL/Verilog/SystemVerilog compiler
  • coreir
    • LLVM-style hardware compiler with first class support for generators
  • dfiant
    • Dataflow Hardware Descripition Language
  • firrtl
    • Intermediate Representation for RTL
  • halide
    • Language for fast, portable data-parallel computation
  • halide-to-hardware
    • Hardware generator combining halide and coreir
  • hdlconvertor
    • Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4
  • livehd
    • Infrastructure for live interactive synthesis and simulation
  • llhd
    • Intermediate representation for digital circuit descriptions
  • magma
    • Python based hardware design language
  • matchlib
    • SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL
  • matchclib_connections
    • SystemC library implementing latency-insensitive channels for use by High-Level synthesis tools.
  • myhdl
    • Python baed hardware description and verification language
  • panda
    • High level synthesis (HLS) C/C++ framework
  • pipelinec
    • C-like hardware description language (HDL) with automatic pipelining
  • pygears
    • Python based hardware design framework
  • pymtl3
    • Python hardware generation, simulation, and verification framework
  • pyrtl
    • Python integrated design and soimulation framework
  • pysysc
    • Python package to make SystemC usable from Python
  • pyverilog
    • Python design toolkit for Verilog HDL
  • rohd
    • Dart based framework for describing and verifying hardware
  • silice
    • Language that simplifies prototyping and writing algorithms on FPGA architectures
  • slang
    • Library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code
  • sodaopt
    • Leverages mlir to extract, optimize, and translate high-level code snippets into LLVM IR for use by high-level synthesis tools
  • spinalhdl
    • Scala based HDL
  • spydrnet
    • Framework for analyzing and transforming Verilog netlists
  • surelog
    • SystemVerilog IEEE 2017 Pre-processor, Parser, Elaborator, UHDM Compiler
  • sv-parser
    • SystemVerilog IEEE 1800-2017 parser library
  • sv2v
    • SystemVerilog to Verilog conversion
  • systemc
    • SystemC system design and verification language that spans hardware and software
  • uhdm
    • Unversal object model for IEEE SystemVerilog designs
  • verible
    • Suite of SystemVerilog developer tools, including a parser, style-linter, and formatter
  • verilogger
    • Mixed-Paradigm Hardware Construction Framework
  • verik
    • Kotlin based hardware description language
  • xls
    • Google framework for hardware synthesis

Build Systems

  • bazelhdl
    • Bazel based hdl build system
  • bender
    • Dependency management tool for hardware projects.
  • chipyard
    • Agile RISC-V SoC Design Framework.
  • cocoon
    • An infrastructure for integrated EDA
  • edalize
    • An abstraction library for interfacing EDA tools.
  • f4pga
    • Architecture definitions of FPGA hardware
  • fusesoc
    • Package manager and build abstraction tool for FPGA/ASIC development.
  • hammer
    • Agile physical design component part of UC Berkeley Chipyard framework.
  • hwtBuildsystem
    • Library of utils for interaction with the vendor tools.
  • legoHDL
    • Command line HDL package manager and development tool.
  • mflowgen
    • Modular flow specification and build-system generator for ASIC and FPGA design-space exploration.
  • siliconcompiler
    • Build system that automates translation from source code to silicon.

Generators

  • bag
    • Berkeley analog layout generator
  • esp
    • Design platform for heterogeneous SoC architecture and IP
  • fabulous
    • FPGA fabric generator
  • fftgenerator
    • Chisel based FFT generator
  • garnet
    • CGRA generator
  • gemmini
    • Spatial array machine learning accelerator generator
  • lake
    • Synthesizable memory generator
  • litex
    • Framework for FPGA and soc development
  • openfasoc
    • Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits
  • openfpga
    • FPGA IP Generator
  • openram
    • Static random access memory (SRAM) compiler.
  • prga
    • Python based FPGA fabric generator
  • pymtl3-net
    • Cornell parameterizable OCN (on-chip network) generator
  • revenoc
    • Configurable HDL NoC (Network-On-Chip) generator
  • rggen
    • Configuration and status register generator
  • rocket
    • Rocket chip chisel based generator
  • spiral
    • Spiral based FFT generator
  • systemrdl
    • Generic compiler front-end for Accellera's SystemRDL 2.0 register description language
  • tce
    • Application-specific instruction-set processor (ASIP) toolset for design and programming of customized co-processors
  • kaktus2dev
    • Graphical EDA tool based on the IP-XACT standard

Analog Design

  • xschem
    • Schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog

Board Design

  • boardview
    • Reads KiCAD PCB layout files and writes ASCII Boardview files
  • datasheet-scrubber
    • Utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information
  • kicad
    • Board design framework

Logic Synthesis

  • abc
    • System for Sequential Logic Synthesis and Formal Verification
  • lsoracle
    • Famework built on EPFL logic synthesis libraries.
  • lstools
    • Showcase examples for EPFL logic synthesis libraries
  • mockturtle
    • C++ logic network library
  • yosys
    • Yosys Open SYnthesis Suite

ASIC Layout

  • align
    • Automatic layout generator for analog circuits
  • coriolis
  • dreamplace
    • Deep learning toolkit-enabled VLSI placement
  • gds3d
    • Reads GDSII layout and renders in 3D.
  • gdsfactory
    • Python package to generate GDS layouts.
  • gdstk
    • Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.
  • gdspy
    • Python module for creating GDSII stream files, usually CAD layouts.
  • klayout
    • Layout viewer
  • magic
    • VLSI Layout Tool
  • magical
    • Machine Generated Analog IC Layout
  • netgen
    • LVS tool for comparing SPICE or verilog netlists
  • openlane
    • Automated ASIC flow scripts based on openroad, yosys, magic, netgen.
  • openroad
    • Complete RTL2GDS platform
  • phidl
    • Python GDS layout and CAD geometry creation

FPGA Layout

  • nextpnr
    • FPGA place and route tool
  • vtr
    • FPGA place and route tool

Formal Verification

  • boolector
    • SMT solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
  • cvc5
    • SMT automatic theorem prover
  • ilang
    • Princeton modeling and Verification Platform for SoCs using ILAs
  • pono
    • Extensible SMT-based model checker implemented in C++.
  • sby
    • Front-end for Yosys-based formal verification flows.
  • z3
    • Microsoft research theorem prover.

Simulation and Analysis

  • anasysmod
    • Framework for FPGA emulation of mixed-signal systems
  • cocotb
    • Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  • dromajo
    • RISC-V RV64GC functional emulator
  • epiphany-dv
    • SystemC based constrained random verification environment for Epiphany
  • gem5
    • Modular simulator platform for computer-system architecture research
  • ghdl
    • VHDL 2008/93/87 simulator
  • icarus
    • Verilog IEEE-1364 simulator
  • hotspot
    • Thermal modeleing tool for use in architectural studies
  • libsystemctlm-soc
    • SystemC/TLM-2.0 Co-simulation framework
  • msdsl
    • Automatic generation of real number models from analog circuits
  • ngspice
    • Spice simulator
  • opensta
    • Signoff quality STA engine used by OpenRoad
  • opentimer
    • High perormance static timing analysis
  • osvvm
    • A VHDL verification framework, utility library, verification component library, and a simulator independent scripting flow
  • qemu
    • Generic and open source machine & userspace emulator and virtualizer
  • qucs
    • Itegrated circuit simulator with Graphical User Interface
  • pact
    • Thermal Simulator
  • pyuvm
    • SystemVerilog UVM written in Python
  • SimulIDE
    • SimulIDE is a simple real-time electronic circuit simulator
  • svlint
    • SystemVerilog linter
  • svlint-action
    • GitHub action for svlint
  • svreal
    • Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  • renode
    • Generic and open source machine emulator (including multi-part and peripheral) designed to run unmodified firmware which includes co-simulation with RTL simulators.
  • verilator
    • SystemVerilog simulator and lint system.
  • vunit
    • Unit testing framework for VHDL/SystemVerilog
  • xyce
    • Parallel spice simulator from Sandia national labs

Waveform viewers

  • gtkwave
    • GTK+ based VCD waveform viewer
  • konata
    • Instruction pipeline visualizer for Gem5
  • sigrok
    • Portable, cross-platform, sinal analysis software suite (logic analyzers, scopes, multimeters, and more)
  • simview
    • Text-based SystemVerilog design browser and waveform viewer
  • sootty
    • Command-line tool for displaying vcd waveforms

Benchmark Circuits

  • epfl-benchmarks
    • Combinational Benchmark Suite for logic synthesis
  • bsg_pipeclean_suite
    • Collection of designs used to stress test new CAD flows
  • corescore
    • Benchmark for FPGAs and their synthesis/P&R tools
  • rdf-2019
    • IEEE CEDA eda benchmark flow
  • opdb
    • Princeton design benchmark generators
  • sv-tests
    • SystemVerilog compliance test suite

Documentation

  • graphviz
    • Python library for graph cration and rendering in DOT language
  • pcbdraw
    • Convert KiCAD board into 2D drawing suitable for pinout diagrams
  • pinion
    • Generate interactive Diagrams for your PCBs
  • pinout
    • Python package that generates hardware pinout diagrams as SVG images
  • sphinx
    • Document builder
  • symbolator
    • HDL symbol generator
  • wavedrom
    • Digital timing diagram rendering engine
  • wavedrompy
    • Python comptabled Wavedrom module

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